SELCC=RISING_EDGE_OF_CAP0_, CTM=TIMER_MODE_EVERY_RI, CIS=CT16BN_CAP0
Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
| CTM | Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer’s Prescale Counter (PC), or clear PC and increment Timer Counter (TC). 0 (TIMER_MODE_EVERY_RI): Timer Mode: every rising PCLK edge 1 (COUNTER_MODE_TC_IS_): Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. 2 (COUNTER_MODE_TC_IS_): Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. 3 (COUNTER_MODE_TC_IS_): Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. |
| CIS | Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000. 0 (CT16BN_CAP0): CT16Bn_CAP0 1 (CT16BN_CAP1): CT16Bn_CAP1 |
| ENCC | Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. |
| SELCC | When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero. 0 (RISING_EDGE_OF_CAP0_): Rising Edge of CAP0 clears the timer (if bit 4 is set). 1 (FALLING_EDGE_OF_CAP0): Falling Edge of CAP0 clears the timer (if bit 4 is set). 2 (RISING_EDGE_OF_CAP1_): Rising Edge of CAP1 clears the timer (if bit 4 is set). 3 (FALLING_EDGE_OF_CAP1): Falling Edge of CAP1 clears the timer (if bit 4 is set). 4 (RESERVED_): Reserved. 5 (RESERVED_): Reserved. 6 (RESERVED_): Reserved. 7 (RESERVED_): Reserved. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |